2018-08-15 05:19:38 +00:00
|
|
|
/* Copyright 2018 Jack Humbert
|
|
|
|
* Copyright 2018 Yiancar
|
|
|
|
*
|
2019-11-05 07:19:21 +00:00
|
|
|
* This program is free software: you can redistribute it and/or modify
|
2018-08-15 05:19:38 +00:00
|
|
|
* it under the terms of the GNU General Public License as published by
|
2019-11-05 07:19:21 +00:00
|
|
|
* the Free Software Foundation, either version 2 of the License, or
|
2018-08-15 05:19:38 +00:00
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* This library follows the convention of the AVR i2c_master library.
|
|
|
|
* As a result addresses are expected to be already shifted (addr << 1).
|
|
|
|
* I2CD1 is the default driver which corresponds to pins B6 and B7. This
|
|
|
|
* can be changed.
|
|
|
|
* Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
|
|
|
|
* STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file.
|
|
|
|
*/
|
2019-07-16 08:30:53 +00:00
|
|
|
#pragma once
|
2018-08-15 05:19:38 +00:00
|
|
|
|
|
|
|
#include "ch.h"
|
|
|
|
#include <hal.h>
|
|
|
|
|
2019-12-13 01:20:04 +00:00
|
|
|
#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F4XX) || defined(STM32L0xx) || defined(STM32L1xx)
|
2019-08-30 18:19:03 +00:00
|
|
|
# define USE_I2CV1
|
2019-07-16 08:30:53 +00:00
|
|
|
#endif
|
|
|
|
|
2019-06-01 23:04:09 +00:00
|
|
|
#ifdef I2C1_BANK
|
2019-08-30 18:19:03 +00:00
|
|
|
# define I2C1_SCL_BANK I2C1_BANK
|
|
|
|
# define I2C1_SDA_BANK I2C1_BANK
|
2019-01-27 05:25:59 +00:00
|
|
|
#endif
|
2019-06-01 23:04:09 +00:00
|
|
|
|
|
|
|
#ifndef I2C1_SCL_BANK
|
2019-08-30 18:19:03 +00:00
|
|
|
# define I2C1_SCL_BANK GPIOB
|
2019-06-01 23:04:09 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef I2C1_SDA_BANK
|
2019-08-30 18:19:03 +00:00
|
|
|
# define I2C1_SDA_BANK GPIOB
|
2019-06-01 23:04:09 +00:00
|
|
|
#endif
|
|
|
|
|
2019-01-27 05:25:59 +00:00
|
|
|
#ifndef I2C1_SCL
|
2019-08-30 18:19:03 +00:00
|
|
|
# define I2C1_SCL 6
|
2019-01-27 05:25:59 +00:00
|
|
|
#endif
|
|
|
|
#ifndef I2C1_SDA
|
2019-08-30 18:19:03 +00:00
|
|
|
# define I2C1_SDA 7
|
2019-01-27 05:25:59 +00:00
|
|
|
#endif
|
|
|
|
|
2019-12-13 01:20:04 +00:00
|
|
|
#if defined(STM32F1XX) || defined(STM32F1xx)
|
|
|
|
# define USE_GPIOV1
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef USE_GPIOV1
|
|
|
|
// The default PAL alternate modes are used to signal that the pins are used for I2C
|
|
|
|
# ifndef I2C1_SCL_PAL_MODE
|
|
|
|
# define I2C1_SCL_PAL_MODE 4
|
|
|
|
# endif
|
|
|
|
# ifndef I2C1_SDA_PAL_MODE
|
|
|
|
# define I2C1_SDA_PAL_MODE 4
|
|
|
|
# endif
|
|
|
|
#endif
|
|
|
|
|
2019-07-16 08:30:53 +00:00
|
|
|
#ifdef USE_I2CV1
|
2019-08-30 18:19:03 +00:00
|
|
|
# ifndef I2C1_OPMODE
|
|
|
|
# define I2C1_OPMODE OPMODE_I2C
|
|
|
|
# endif
|
|
|
|
# ifndef I2C1_CLOCK_SPEED
|
|
|
|
# define I2C1_CLOCK_SPEED 100000 /* 400000 */
|
|
|
|
# endif
|
|
|
|
# ifndef I2C1_DUTY_CYCLE
|
|
|
|
# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
|
|
|
|
# endif
|
2019-07-16 08:30:53 +00:00
|
|
|
#else
|
2019-08-30 18:19:03 +00:00
|
|
|
// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
|
|
|
|
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
|
|
|
|
# ifndef I2C1_TIMINGR_PRESC
|
2019-10-31 16:19:57 +00:00
|
|
|
# define I2C1_TIMINGR_PRESC 0U
|
2019-08-30 18:19:03 +00:00
|
|
|
# endif
|
|
|
|
# ifndef I2C1_TIMINGR_SCLDEL
|
2019-10-31 16:19:57 +00:00
|
|
|
# define I2C1_TIMINGR_SCLDEL 7U
|
2019-08-30 18:19:03 +00:00
|
|
|
# endif
|
|
|
|
# ifndef I2C1_TIMINGR_SDADEL
|
2019-10-31 16:19:57 +00:00
|
|
|
# define I2C1_TIMINGR_SDADEL 0U
|
2019-08-30 18:19:03 +00:00
|
|
|
# endif
|
|
|
|
# ifndef I2C1_TIMINGR_SCLH
|
2019-10-31 16:19:57 +00:00
|
|
|
# define I2C1_TIMINGR_SCLH 38U
|
2019-08-30 18:19:03 +00:00
|
|
|
# endif
|
|
|
|
# ifndef I2C1_TIMINGR_SCLL
|
2019-10-31 16:19:57 +00:00
|
|
|
# define I2C1_TIMINGR_SCLL 129U
|
2019-08-30 18:19:03 +00:00
|
|
|
# endif
|
2019-06-01 23:04:09 +00:00
|
|
|
#endif
|
|
|
|
|
2018-08-15 05:19:38 +00:00
|
|
|
#ifndef I2C_DRIVER
|
2019-08-30 18:19:03 +00:00
|
|
|
# define I2C_DRIVER I2CD1
|
2018-08-15 05:19:38 +00:00
|
|
|
#endif
|
|
|
|
|
2019-04-16 03:32:57 +00:00
|
|
|
typedef int16_t i2c_status_t;
|
|
|
|
|
|
|
|
#define I2C_STATUS_SUCCESS (0)
|
2019-08-30 18:19:03 +00:00
|
|
|
#define I2C_STATUS_ERROR (-1)
|
2019-04-16 03:32:57 +00:00
|
|
|
#define I2C_STATUS_TIMEOUT (-2)
|
|
|
|
|
2019-08-30 18:19:03 +00:00
|
|
|
void i2c_init(void);
|
2019-04-16 03:32:57 +00:00
|
|
|
i2c_status_t i2c_start(uint8_t address);
|
|
|
|
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
|
|
|
|
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
|
2019-08-30 18:19:03 +00:00
|
|
|
i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t* tx_body, uint16_t tx_length, uint8_t* rx_body, uint16_t rx_length);
|
2019-04-16 03:32:57 +00:00
|
|
|
i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
2019-07-16 08:36:23 +00:00
|
|
|
i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
2019-08-30 18:19:03 +00:00
|
|
|
void i2c_stop(void);
|